Subtask 3.3.3: Guidelines for eco-design

By exploiting the techniques developed in Tasks 3.3.1 and 3.3.2, this subtask identifies the best practices to guide the eco-design of durable ECS. The objective is the reduction of environmental impacts, while taking into account the other multiple constraints of ECS, and e-waste. A preliminary version of the techniques and guidelines for eco-design will be delivered in Month M0+22. The final report of the implementation of eco-design tools for 6R and the guidelines description will be released in Month M0+36.

Role of partners

- CEA participates in the three subtasks of Task 3.3. In Task 3.3.1, CEA will develop a dedicated and simplified tool to evaluate the impacts of power electronics to reduce their environmental impacts and e-waste. The tool is meant to be used by any electrical engineers non-expert in environmental impact evaluation. The tool will implement the decision making process, considering analysis of LCA outputs (performed by CEA), and considering design rules provided by other partners involved in this task. CEA will also work on techniques for environmental assessment targeted to Integrated Circuits. In Task 3.3.2, CEA will develop techniques for the eco-reliable design of sustainable and resilient Integrated Circuits. CEA will integrate in the design flow the metrics defined in Task 3.2 about the 6R, while taking into account the standard constraints of circuits (performance, energy consumption, area). A mathematical optimization model will be proposed to provide efficient design strategies, using techniques from Operational Research and Combinatorial Optimisation, and will be used for the development of an optimization algorithm. CEA will also focus on memory/storage systems, for which the impact of several fault-tolerance, error-tolerance and monitoring techniques will be investigated with respect to their environmental influence. In Task 3.3.3, CEA will exploit the results of the previous tools to steer the user toward the 6R best practices to apply during the design phase. Other guidelines will be provided specifically for Integrated Circuits to define the best configuration for multi-objective design including environmental impact and the 6R, in compliance with the standard requirements analysed in WP5.

- ACORDE will support the implementation of tools in terms of API, databases and processes to integrate circular electronics in ACORDE design processes.

- ANIAH will made available their lifetime modelling capacities through their integration:

o In Dassault Systèmes suite (3DEXPERIENCE platform)

o In EECONE s EcoDesign Tools

o More widely, through an API usage (including cloud and customer-premises access)

Those integrations include access to the functionality, but also to our GUI that can be embedded as a web widget.

- ARCELIK will provide specification of the eco-design system tool based on specification and requirements for electronic components in household appliances. Arcelik will provide data for the system-level eco-design tool developed by OZU. Also, Arcelik will test and validate it.

- AT&S will participate in the development of an LCA Process including a LCA Tool to assess the environmental impact and related e-waste potential of PCB production based on the actual process situation and related material consumption. Based on the results and ratings of the LCA Tool, AT&S will develop an Eco reliability guideline to support a balanced design between lifetime and resource efficiency to generate less e-waste. Furthermore, AT&S will describe eco-design guidelines for PCB design to support more resource efficient and sustainable PCB and substrate design to minimise the environmental impact of ECS.

- Dassault Systèmes will participate in the evaluation of existing Lifecycle Assessment tools, including their own 3DEXPERIENCE LCA solution (sustainable innovation manager) in the frame of subtask 3.3.1. Dassault Systèmes will define and develop related 3DEXPERIENCE platform tools enhancements (eco-design solution for 6R), targeting beyond 2022 status-quo and initiates move toward zero e-waste.

- DTI will optimise the electrical design process within standard and printed electronics and participate in the development of tools for eco design. It will be in collaboration with Melsentech from WP4.

- ECODC will support RISE on the contribution of the eco-design guidelines with reference to ICT equipment that is destined for European data centres. The guidelines will also be supported by a case study led by ECODC.

- Fraunhofer will work on thermal management as part of eco-design for highly integrated systems such as multi-chip packages. Durability and reliability are thus addressed and harmonised with eco-design as eco-reliability. Generalised guidelines will be extracted, and test cases will be refined.

- HUA will design, develop and implement knowledge-based, cognitive optimization algorithms for adding resilience and increasing sustainability. The algorithms will form part of a custom-developed software tool for assessing, monitoring, and improving (based on pre-defined KPIs) reliability through e-waste management, in green ECS and related devices. The resulting software tool will be developed in common with partner SSOL.

- IFAG (Infineon) will evaluate whether useful guidelines/input to the system-level eco-design tool can be derived from the simulation of packages with aged material layers.

- INP-GRE, CNRS and UGA will contribute to system-level eco-design tool in:

o defining specifications.

o developing the questionnaire and the subsequent design propositions/orientation with respect to the various 6R scenario

o developing the subpart of the tool regarding the housing (mechanical/thermal) to be able to take into account its impact on the overall design with respect to environmental impacts;

o applying the tool to a case study for power electronics applications (UC2 and 7) in close relation with developments in WP4 where different design approaches will be addressed regarding the outputs of the tool.

CNRS and UGA will bring expertise and support to carry on this R&D activity. The associated deliverable will be common.

- IMEC will develop imec.netzero, a Virtual Fab tool for the quantification of the environmental impact of Integrated Circuit chip manufacturing in a high volume foundry. Three activities will be developed. (1) Virtual Fab tool construction through Fab data collection (process details, process flows, materials) and Fab model implementation. (2) Virtual Fab result interpretation and benchmarking. Validation of methodologies with other consortium partners (CEA). (3) As task leader for subtask 3.3.1, IMEC will coordinate the different partners contributing to the environmental assessment tools, toward a common implementation on the Eco-design platform developed in Task 3.1. Finally, in WP5, the Virtual Fab tool will also be formatted as a publicly available web application called imec.netzero that will provide high-quality data to academic researchers, IC product developers and policy makers.

- UL-IMF will provide specification of the eco-design system tool based on technical requirements for Experimental Technological Line (semiconductor microfabrication facility by IMiF and EECONE partners). Use case support in tool crosscheck and validation.

- Nerosubianco will participate in the validation of the ecodesign tools and the analysis of WP3 related Use Cases (observe application of technologies, check how the initial problems have been solved, evaluate its replicability)

- OZU will work on Software implementation of system-level eco-design tool to make it easier to use for non-LCA-experts. Development of plug-ins that would make eco-design tool able to incorporate use-case (or industry) specific constraints and needs (i.e., the eco-design tool would be general enough to be applicable to all use cases but would also be flexible enough to accommodate specific needs). OZU will contribute to the development of a dedicated and simplified tool for electronics at system level to reduce e-waste and environmental impacts. The tool is meant to be used by any electrical engineer who is non-expert in environmental impact evaluation. It provides a bridge between eco-design and traditional electronics design procedure and aims to help choosing with multi-parameter objectives (cost, performance, e-waste, environmental impacts).

- RISE will provide contributions to system-level eco-design tool and guidelines with particular reference to supporting eco-design labelling of servers installed in European data centres

- SSOL will work on subtask 3.3.2 Eco-reliable tools: Design and development of algorithms to increase reliability in green ECS and related devices for e-waste management, design, development and implementation of algorithms for predictive maintenance (to partner up with CEA / Aniah / Fraunhofer).

- SVS will use systems level eco-design tools and guidelines to build optimised 3D CADD models of data server racks to support UC 07. Swiss Vault will aim to build components for data server racks based on the outcome data (from above tasks and corresponding data from Work packages 2 and 4) to demonstrate proof of concept products. Swiss Vault will work with e-waste recyclers (external vendors) to quantify e-waste production from rack systems. Swiss Vault will incrementally improve product design, test using the standard recycling protocol for materials recycling, and benchmark at each step for improvement of recovery with objective to attain Zero Waste.

- STGNB2 SAS has in place an Eco-design checklist mainly focusing on power efficiency and low-carbon footprint and will contribute to improve the process to integrate better the inputs / needs from other stakeholders (recycling companies, downstream...), especially to update criterions to improve product end of life considerations at the design phase.

ST has been performing LCA on its products for over ten years and is currently updating its tools for more accuracy and scalability. One of the difficulties of performing LCA (especially for electronics sector where there is generally a long chain of suppliers and diluted responsibilities) is to assess the steps that are outside of the organisation, ie upstream (ie input materials) and downstream (ie use phase and end of life). STMicroelectronics will provide useful information to upstream / downstream stakeholders for their own LCA models improve the modelling of environmental impact at the end of life of ST products. ST also targets to contribute to standardising methodologies for more comparability by assessing for example the feasibility of a PEFCR for electronics sector for example (Product Environmental Footprint Category Rules, as proposed by European Commission).

- TST, Through the proposed Use-Case (Temperature Soil Probe for Agriculture) and its accumulated experience as IoT solution provider, they will provide requirements and contributions for the development of a tool focused on the utilisation of small lithium batteries to power IoT devices.

- UCLouvain will contribute to a streamlined system-level LCA methodology for systems with limited information about the internal architecture and bill-of-material, applied to the counter-evaluation of LCA environmental impacts of CPE.

- VITESCO will specify the eco-design tool for the power electronic use case from the automotive industry and check the validity of the tool (Report of evaluation of the eco-design tool).

- 4MOD will support the development of the Environmental assessment tools: specifications providing use case of a remote control and small connected objects. It will include the validation of LCA results against existing LCA of their products following the ISO 14040/44 standard.