Subtask 5.1.3 SWOT analysis on Green Electronics/6R approaches
STM and CEA will be key contributors in this subtask.Senior IC architects will perform a critical review of current state-of-the-art practices covering different circular strategies for electronics. To this end, a series of focused interviews will be performed with circular electronics economic operators to identify the current barriers, difficulties, and future needs that might be lifted using new IC functionality. A particular focus will be placed on identifying informational barriers currently limiting 6R strategies, which might be lifted thanks to the upcoming Digital Product Passport. The scope of this study will cover system architecture (choice of interfaces and functionality that make sense to be reused), packaging (investigating barriers for dis-assembly and re-assembly), integrated circuit architecture (ensuring the lifetime of the circuit at the transistor/circuit level) and test (both initial and online diagnostics mechanisms).
The study will also review digital technologies (e.g., data sharing platforms) which promote and enable 6R in electronics.
Along with this IC-level study, system-level research will be performed among the EECONE partners and some European industrials actors to identify:
- their level of expertise in circular economy and eco-design.
- the circular economy and eco-design strategies they developed.
- the economic impacts of their choices.
Brainstorming and sharing the waste management process for a zero waste roadmap alignment. The main objective of this activity is to identify and share among partners ideas for a new "open minded" approach to the sustainability of electronics and align roadmaps among partners for a stronger ecosystem development. To perform this task a fact-based approach will be used, as: